Image sensor and method of manufacturing the same

ABSTRACT

Disclosed is a method of manufacturing an image sensor having light sensitivity over a photodiode equal in area to that of a unit pixel. The image sensor includes an image sensor comprising: a first semiconductor substrate doped with a first conductive dopant; a first diffusion layer formed in the semiconductor substrate and doped with a second conductive dopant; a second diffusion layer formed in the semiconductor substrate adjacent the first diffusion layer and having a width wider than a width of the first diffusion layer; a third diffusion layer doped with the first conductive dopant and formed at an exposed surface of the semiconductor substrate in the first diffusion layer; a gate electrode formed on the exposed surface and having a first edge adjacent to the third diffusion layer; and a fourth diffusion layer doped with the second conductive dopant and formed at the exposed surface adjacent a second edge of the gate electrode, the fourth diffusion layer defining a gap with the second diffusion layer.

FIELD OF THE INVENTION

[0001] The present invention relates to a method of manufacturing asemiconductor device and, more particularly, to a method ofmanufacturing a complementary metal oxide semiconductor (CMOS) imagesensor.

DESCRIPTION OF RELATED ART

[0002] Generally, in a charge couple device (CCD) or a complementarymetal oxide semiconductor (CMOS) image sensor, a photodiode (PD)functions as a converter to change an incident light into an electricsignal. Ideally the quantum efficiency of this conversion is 1 at allwavelengths of light, that is, the incident light is gathered in thephotodiode and entirely converted into electric signals.

[0003]FIG. 1 is an equivalence circuit diagram of a general CMOS imagesensor unit pixel (UP). The equivalent circuit includes a photodiode(PD) and four n-channel metal oxide semiconductor (NMOS) transistors(Tx, Rx, Dx and Sx). The four NMOS transistors are comprised of atransfer transistor (Tx), a reset transistor (Rx), a drive transistor(Dx) and a select transistor (Sx). There is also a load transistor (Vb)capable of reading an output signal external to the UP.

[0004]FIG. 2 is a layout diagram of the CMOS image sensor UP shown inFIG. 1. FIG. 3 is a cross-sectional view showing a conventional CMOSimage sensor taken along the line A-A′, of FIG. 2. Referring to FIGS. 2and 3, a p⁻-epitaxial (p⁻-epi) layer is grown on a p⁺⁺ substrate(p⁺⁺-sub) and a field oxide layer (FOX) is formed in a predeterminedportion of the p⁻-epitaxial layer. A p-well is formed in a predeterminedportion of the p⁻-epitaxial layer and a drive gate (Dx) and a selectgate (Sx) are formed within the p-well. On the p-epitaxial layer, wherethe p-well is not formed, a transfer gate (Tx) and a reset gate (Rx) areformed, and a photodiode (PD) is formed between one-side of a transfergate (Tx) and the FOX.

[0005]FIG. 4 is a cross-sectional view showing the photodiode andtransfer gate of a conventional CMOS image sensor along a line B-B′ inFIG. 2. Referring to FIG. 4, in a PNP-type photodiode, a p⁻-epitaxiallayer 12 is formed on a p⁺⁺-substrate 11, a deep n⁻-diffusion layer 13is formed within the p⁻-epitaxial layer 12. A shallow p⁰-diffusion layer14 is formed on the deep n⁻-diffusion layer 13 and at a portion ofsurface of the p⁻-epitaxial layer 12.

[0006] The transfer gate (Tx) is formed on the p⁻-epitaxial layer 12 atan edge of the photodiode (PD), and a source/drain of a transfer gate(Tx), in the form of a floating sensing node 15, is formed within thep⁻-epitaxial layer 12. Also, a high concentration p⁺-doping layer 16 isformed for preventing a punchthrough on a bottom portion of the FOXlayer at the floating sensing node 15.

[0007] In the above-mentioned conventional method, when a reverse-biasis generated between the n⁻-diffusion layer 13 of the photodiode and thesurrounding p-region (p⁰-diffusion layer 14 and p⁻-epitaxial layer 12)and when a dopant concentration in the n⁻-diffusion layer 13 and thep-region are properly controlled, the n⁻-diffusion layer 13 is fullydepleted and a depletion region diffuses below the n⁻-diffusion layer 13and into the p⁻-epitaxial layer 12. The greater the reverse-bias, thefurther into the p⁻-epitaxial layer 12 the depletion region extends.Reference numeral ‘h1’ shows a depth of a depletion layer.

[0008] In the image sensor with the photodiode PD, an electrical outputsignal (voltage or current) is obtained by removing electrons stored inthe PD. Accordingly, since the greatest output signal is in proportionalto the number of electrons removed from the PD, the number of electronsgenerated and stored within the PD by light should be increased toincrease the amount of the output signal.

[0009] As above described, an electron generated in a depletion layer ofa pinned PD is changed into an electrical signal (voltage or current).To form a depletion layer that extends sufficiently deep enough from asurface, an ion injection is carried out so that a dopant concentrationof a surface layer (p⁰-diffusion layer 14) is much higher than that ofthe layer(s) below it (n⁻-diffusion layer 13 and p⁻-epitaxial layer 12).

[0010] Meanwhile, in the above-mentioned conventional method, electronhole pairs (EHPs) are generated in the n⁻-diffusion layer 13, which is adepletion layer. of the pairs, holes (H) flow into the p⁺⁺ substrate 11,and electrons (e) are stored and moved into the floating sensing node 15(or a floating diffusion region) through a transfer gate (Tx). From thiscurrent flow, an electrical signal representing image data may becreated.

[0011] The above-mentioned conventional method, unfortunately limits thearea of the PD to an area much smaller than that of the unit pixel UP.Accordingly, the generation rate and storage area is small and does nothave a high light sensitivity. That is, the n⁻-diffusion layer 13 isformed only in a region where light (L) incident on the PD may beconverted to image data but, other light (e.g., L₁ and L₂), that isincident other region outside the PD, will not be so converted. As aresult, the light sensitivity of other region is substantially lowerthan that of the region over which (L) incident, that is, if it is lightsensitive at all.

SUMMARY OF THE INVENTION

[0012] In accordance with one aspect of the present invention, there isprovided an image sensor comprising: a first semiconductor substratedoped with a first conductive dopant; a first diffusion layer formed inthe semiconductor substrate and doped with a second conductive dopant; asecond diffusion layer formed in the semiconductor substrate adjacentthe first diffusion layer and having a width wider than a width of thefirst diffusion layer; a third diffusion layer doped with the firstconductive dopant and formed at an exposed surface of the semiconductorsubstrate in the first diffusion layer; a gate electrode formed on theexposed surface and having a first edge adjacent to the third diffusionlayer; and a fourth diffusion layer doped with the second conductivedopant and formed at the exposed surface adjacent a second edge of thegate electrode, the fourth diffusion layer defining a gap with thesecond diffusion layer.

[0013] In accordance with another aspect of the present invention, thereis provided an image sensor, wherein the first conductive dopant is ap-type dopant and the second conductive dopant is a n-type dopant.

[0014] In accordance with still another aspect of the present invention,there is provided a method of manufacturing an image sensor, comprisingthe steps of: a) forming a first diffusion layer within a semiconductorsubstrate, the semiconductor substrate being doped of a first conductivedopant and the first diffusion layer being doped of a second conductivedopant; b) forming a gate electrode on the semiconductor substrate, thegate electrode having a first sidewall and a second sidewall; c) forminga second diffusion layer in the semiconductor substrate adjacent thefirst diffusion layer; d) forming a first spacer at the first sidewalland a second spacer at the second sidewall; e) forming a third diffusionlayer in the first diffusion layer adjacent the first spacer, the thirddiffusion layer being doped with the first conductive dopant; and f)forming a fourth diffusion layer within the semiconductor substrateadjacent the second spacer, the fourth diffusion layer being doped withthe second conductive dopant.

[0015] In accordance with further still another aspect of the presentinvention, there is provided a method of manufacturing an image sensor,comprising the steps of: a) forming a first diffusion layer within asemiconductor substrate, the semiconductor substrate being doped of afirst conductive dopant and the first diffusion layer being doped of asecond conductive dopant; b) forming a gate electrode on thesemiconductor substrate, the gate electrode having a first sidewall anda second sidewall; c) forming a second diffusion layer in thesemiconductor substrate adjacent the first diffusion layer; d) forming afirst spacer at the first sidewall and a second spacer at the secondsidewall; e) forming a third diffusion layer in the first diffusionlayer adjacent the first spacer, the third diffusion layer being dopedwith the first conductive dopant; f) forming a fourth diffusion layerwithin the semiconductor substrate adjacent the second spacer, thefourth diffusion layer being doped with the second conductive dopant;and g) forming a fifth diffusion layer between the fourth diffusionlayer and the second diffusion layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other objects and aspects of the disclosure will become apparentfrom the following description of the embodiments with reference to theaccompanying drawings, in which:

[0017]FIG. 1 is an equivalence circuit diagram illustrating a generalcomplementary metal oxide semiconductor (CMOS) image sensor;

[0018]FIG. 2 is a plain diagram showing a layout of the CMOS imagesensor shown in FIG. 1;

[0019]FIG. 3 is a cross-sectional view showing a conventional CMOS imagesensor device taken along the line A-A′ of FIG. 2;

[0020]FIG. 4 is a cross-sectional view showing a conventional CMOS imagesensor device taken along the line B-B′ of FIG. 2;

[0021]FIG. 5 is a cross-sectional view showing a CMOS image sensordevice in accordance with a first embodiment;

[0022]FIGS. 6a to 6 d are cross-sectional views showing a manufacturingprocess of a CMOS image sensor in accordance with the first embodiment;

[0023]FIG. 7 is a cross-sectional view showing a CMOS image sensordevice in accordance with a second embodiment; and

[0024]FIGS. 8a to 8 d are cross-sectional views showing a manufacturingprocess of a CMOS image sensor in accordance with the second embodiment.

DETAILED DESCRIPTION OF THE INVENTION

[0025] A method of manufacturing an image sensor will be described indetail referring to the accompanying drawings.

[0026]FIG. 5 is a cross-sectional view showing a CMOS image sensordevice having a field insulating layer, a photodiode and a transfer gatein accordance with a first embodiment of the disclosed. By way ofexample, FIG. 5 may be a cross-sectional view of a CMOS image sensor,showing a view similar to that taken along the line B-B′ in FIG. 2.According to a first embodiment, a photodiode (PD′) includes a lowconcentration p⁻-epitaxial layer 22, an n⁻-diffusion layer having firstand second n⁻-diffusion layers 23 a and 23 b and a p⁰-diffusion layer24. The low concentration p⁻-epitaxial layer 22 is an epitaxial layergrown on a p⁺⁺ substrate 21. The first and second n⁻-diffusion layers 23a and 23 b are formed in the p⁻-epitaxial layer 22, and the secondn⁻-diffusion layer 23 b is wider than the first n⁻-diffusion layer 23 a.Further the first n⁻-diffusion layer 23 a is formed on the secondn⁻-diffusion layer 23 b. The p⁰-diffusion layer 24 is formed in an areaof the first n⁻-diffusion layer 23 a so that it is disposed below anexposed surface of the p⁻-epitaxial layer 22 and the second n⁻-diffusionlayer 23 b. The width of the p⁰-diffusion layer 24 is narrower than thatof the second n⁻-diffusion layer 23 b.

[0027] A gate electrode 25 of the transfer gate (Tx) having a spacer 25a is formed on the p⁻-epitaxial layer 22 between the photodiode (PD′)and a floating sensing node 26 where n⁺ dopants are doped.

[0028] The photodiode (PD′), the transfer gate (Tx) and the floatingsensing node 26 are isolated from an adjacent device by a fieldinsulating layer FOX.

[0029] In an operation of the photodiode PD′, when the transfer gate(Tx) and a reset gate (Rx) (not shown) are turned on, a voltage (VDD)from a voltage source is applied to the first n⁻-diffusion layer 23 aand the second n⁻-diffusion layer 23 b, thereby generating a depletionregion. When the n⁻-diffusion layer 23 a and the n⁻-diffusion layer 23 bare in a complete depletion condition (C), a depletion layer depth (h2)results. The depletion layer depth (h2) is much deeper and wider thanthe pk-diffusion layer 24.

[0030] In contrast, in the conventional structure of FIG. 4, a singledeep n⁻-diffusion layer 13 is provided, and under complete depletion,the depletion layer depth is ‘h1’ and the width is ‘d₁’, as shown.Comparing FIG. 4 with FIG. 5, ‘h2’ of FIG. 5 is larger than the ‘h1’ inFIG. 4, because the thickness of the n⁻-diffusion layer of FIG. 5, whichhas the first n⁻-diffusion layer 23 a and the second n⁻-diffusion layer23 b, is much thicker than that of conventional n⁻-diffusion layer 13.Meanwhile, the n diffusion layer 13 of the conventional method and thesecond n⁻-diffusion layer 23 b of the present invention have the samephysical depth and width.

[0031] In the embodiment of FIG. 5, a two-layer n⁻-diffusion layer isformed through a plurality of ion injections having different energylevels to form the n⁻-diffusion layers 23 a and 23 b to form a thickn⁻-diffusion layer. Therefore, the depth and width of the depletionregion are increased in operating the photodiode PD′, and the area ofthe depletion region is increased.

[0032] If the depth and width of the photodiode PD′ depletion region areincreased, the electron generation and storage area in creating imagedata are increased, thereby improving light sensitivity within the imagesensor. In other words, incident light (L) incident upon the photodiodePD′ and light (L₁₁, L₂₁) incident upon other regions of the sensoroutside of the PD′ will be converted to image data due to thesensitivity on the n⁻-diffusion layer 23 a.

[0033] The ion injection energy and the depth of the first n⁻-diffusionlayer 23 a is modulated to avoid forming a short circuit between thefloating sensing node 26 of the n⁺ doped region and the firstn⁻-diffusion layer 23 a when the n⁻-diffusion layer 23 a is completelydepleted.

[0034]FIGS. 6a to 6 d are cross-sectional views showing a manufacturingprocess of a CMOS image sensor in accordance with an embodiment likethat of FIG. 5. Referring to FIG. 6a, a p⁻-epitaxial layer 32 having alow concentration p-type dopant is formed on a p⁺⁺ substrate 31 having ahigh concentration p-type dopant. The p⁻-epitaxial layer 32 is grownsuch that the depth of a depletion region of a photodiode is increasedto obtain higher light sensitivity. Also, a unit pixel cross talkphenomena typically caused by an irregular movement of light electriccharge, is prevented through recombination of the light electric chargeswithin the high concentration p⁺⁺ substrate 31.

[0035] Next, a field insulating layer 33 for insulating adjacent unitpixels or other components is formed in a predetermined part of thep⁻-epitaxial layer 32 with a local oxidation of silicon (LOCOS) method.A photoresist layer is covered on the resulting structure including afield insulating layer 33.

[0036] The photoresist layer is selectively patterned to cover the fieldinsulating layer 33 and a first mask 34, thereby exposing the topsurface of the p⁻-epitaxial layer 32. A low concentration of n-typedopants are ioninjected with high energy to the p⁻-epitaxial layer 32using the first mask 34 as an ion injection mask, and then a firstn⁻-diffusion layer 35 having deep depth and wide area is formed.

[0037] Before forming the above-mentioned the field insulating layer 33and the first n⁻-diffusion layer 35, a p-well may be formed in apredetermined region (not shown) of the p⁻-epitaxial layer 32 to includethe drive gate (Dx) and the select gate (Sx) through a side diffusion bya thermal treatment, similar to that of FIG. 3.

[0038] After forming the first n⁻-diffusion layer 35, a generaltransistor manufacturing process is carried out to form the drive gate(Dx) and the select gate (Sx) of the four gates of the image sensor.That is, within the p-well, an ion injection process of a thresholdvoltage modulating ion, to regulate the threshold voltage of atransistor, and a deep ion injection process of a p-type dopant, toregulate punchthrough characteristics of the device, are performed.These ion injection processes are not performed in a region of thedevice where a photodiode and the source drain of the transfer gate (Tx)are to be formed.

[0039] Referring to FIG. 6b, the mask 34 is striped and a conductivelayer is deposited for forming four gates of the transistor. Aphotoresist layer is covered and patterned via an exposure anddevelopment to form a photoresist pattern (not shown) for forming thegate electrodes. The doping profile of a photodiode determines anelectric charge transfer effect, which can be used to result in adesired thickness for the gate electrodes. Accordingly, a high energyn-type dopant ion injection and a low-energy p-type dopant ion injectionare used for forming the photodiode to one side of a transfer gate (Tx).

[0040] The conductive layer is etched using a photoresist pattern toform the gate electrodes of the transistor(s) of a unit pixel. By way ofexample, the gate electrode 36, shown in FIG. 6B, is a gate electrode ofthe transfer gate (Tx).

[0041] A photoresist layer is covered on the resulting structureincluding the gate electrode 36, and a second mask 37 for ion injectingis applied, and a high energy n-type dopant region is formed byselectively patterning the photoresist layer.

[0042] At this time, one-side of the second mask 37 is arranged in acenter of a transfer gate (Tx) above gate electrode 36, and the otherside is arranged in a predetermined part of the field insulating layer33 without entering in an active region. Subsequently, a lowconcentration n-type dopant is ion injected using the second mask 37 asan ion injection mask, and above the first n⁻-diffusion layer 35, asecond n⁻-diffusion layer 38 is formed on one side of where the transfergate (Tx) is to be formed.

[0043] The second n⁻-diffusion layer 38 is formed by an ion injectionenergy that is much lower than that of the first n⁻-diffusion layer 35.The thickness depth (thickness) is deeper and an area occupied muchlarger for the p⁻-epitaxial layer 32 as compared to the n⁻-diffusionlayer 38.

[0044] A first deep pn junction may be formed in a low concentration ofthe p-epitaxial layer 32, through the ion injection process forming thefirst n⁻-diffusion layer 35 and the second n⁻-diffusion layer 38. Next,an ion injection process for forming the source/drain regions of thefour transistor gates of a unit pixel transistor is performed.

[0045] First, a photoresist layer is applied on the resulting structureand a third mask (not shown) is formed, to form a lightly doped drain(LDD) structure, by patterning the photoresist layer with an exposureand development. A low concentration n-type dopant is then injectedusing the third mask as an ion injection mask within a p-well (notshown) to form the LDD region (not shown). The ion injection is notperformed in a region where the photodiode or the native transistors (Txand Rx) are to be formed.

[0046] Referring to FIG. 6c, after removing the third mask, aninsulating layer or spacer is deposited on the resulting structure, andthen the insulating layer is blanket etched to form a spacer 39contacting the sidewalls of the gate electrode 36 on each of the fourtransistors.

[0047] Diffusion layers 40 a and 40 b are simultaneously formed on anexposed surface of the p⁻-epitaxial layer 32, including the secondn⁻-diffusion layer 38 and the other side of a transfer gate electrode 36by a low energy p-type dopant using a blanket ion injection method. Atthis time, the p⁰-diffusion layer 40 a formed within the secondn⁻-diffusion layer 38 is isolated from the gate electrode 36 by thethickness of the spacer 39.

[0048] The p⁰-diffusion layer 40 b formed on an exposured p⁻-epitaxiallayer 32 is ion-injected with a lower energy n-type dopant, so thep⁰-diffusion layer 40 b has a shallow depth. The p⁰-diffusion layer 40 bis not in contact with the first n⁻-diffusion layer 35, but formed witha p-type dopant as is the p⁻-epitaxial layer 32.

[0049] A second shallow PN junction is formed comprising thep⁰-diffusion layers 40 a and the first and second n⁻-diffusion layers 35and 38 through the above-mentioned ion injection of a p-type dopant. APNP-type photodiode is formed by the p⁻-epitaxial layer 32, the firstand second n⁻-diffusion layers 35 and 38, and the p⁰-diffusion layer 40a.

[0050] Referring to FIG. 6d, a photoresist layer is formed on theresulting structure and a fourth mask 41 is formed to form asource/drain region of the transistor by patterning the resultingstructure with an exposure and a development process.

[0051] A high concentration n-type dopant n⁺ is ion-injected, with thefourth mask 41 as an ion injection mask to form n⁺-diffusion layer 42.As a result, two drive gates (Dx) of the general NMOS transistor, asource/drain region (not shown) of a select gate (Sx), two transfergates (Tx) of the NMOS transistor and a source/drain region (a floatingsensing node) of a reset gate (Rx) may be formed. At this time, thefourth mask 41 exposes, a side of a transfer gate (Tx) and a portion ofthe p-epitaxial layer 32. The fourth mask 41 extends to a center of atransfer gate (Tx). In the region where the photodiode is to be formed,a high concentration n-type dopant is not ion-injected.

[0052] The above-mentioned embodiment forms the first n⁻-diffusionlayers 38, which forms a photodiode of an entire area of a unit pixel,so that an area of the photodiode is largely extended over that ofconventional image sensors.

[0053] The photodiode generates electrons that are converted to imagedata not only from incident light as in a conventional photodiode, butalso from the light incident over the whole area of the unit pixel.

[0054]FIG. 7 is a cross-sectional view showing a CMOS image sensordevice having a field insulating layer, a photodiode and a transfer gatein accordance with a second embodiment. FIG. 7 is a cross-sectional viewof a CMOS image sensor showing a view similar to that taken along thecross-section line B-B′ of FIG. 2. The plain view of the structure ofFIG. 7, like that of FIG. 5, may be like that of the prior art. The sameelements in FIGS. 5 and 7 are denoted with the same reference numerals.

[0055] Referring to FIG. 7, a photodiode according to an embodimentincludes the low concentration p⁻-epitaxial layer 22, the n⁻-diffusionlayer having first and second n⁻-diffusion layers 23 a and 23 b and thep⁰-diffusion layer 24. The low concentration p⁻-epitaxial layer 22 is anepitaxial layer grown on the p⁺⁺ substrate 21. The first and secondn⁻-diffusion layers 23 a and 23 b are formed in the p⁻-epitaxial layer22, and the second n⁻-diffusion layer 23 b has a wider width than thefirst n⁻-diffusion layer 23 a. Further the first n⁻-diffusion layer 23 ais formed on the second n⁻-diffusion layer 23 b. The p⁰-diffusion layer24 is formed in an area of the first n⁻-diffusion layer 23 a so that itis disposed between a surface of the p⁻-epitaxial layer 22 and thesecond n⁻-diffusion layer 23 b. Accordingly, the width of thep⁰-diffusion layer 24 is narrower than that of the second n diffusionlayer 23 b.

[0056] A gate electrode 25 of a transfer gate (Tx) having a spacer 25 ais formed on the p⁻-epitaxial layer 22 adjacent the photodiode PD′, andthen a floating sensing node 26 where n⁺ dopants are doped, is formed ona side of the transfer gate opposite the photodiode PD.

[0057] A p⁺ diffusion layer 27 is formed between the floating sensingnode 26 and the first n⁻-diffusion layer 23 a so as to prevent a shortcircuit between the two, and the photodiode PD′, the transfer gate (Tx)and the floating sensing node 26 are isolated from an adjacent device bythe field insulating layer FOX.

[0058] In operation of a photodiode according to FIG. 7, first, when thetransfer gate (Tx) and the reset gate (Rx) (not shown) are turned on,voltage from a voltage supply VDD is applied to the first n⁻-diffusionlayer 23 a and the second n -diffusion layer 23 b, thereby generating adepletion region, and when the deep first n⁻-diffusion layer 23 a andthe shallow second n⁻-diffusion layer 23 b are in a complete depletion(C) condition, the depletion layer depth (h2) is much deeper and a width(d2) of a depletion layer is much wider than the two layers 23 a and 23b, as shown.

[0059] On the other hand, referring to FIG. 4 of the conventionalmethod, a single deep n⁻-diffusion layer 13 is provided. So if the deepn⁻-diffusion layer 13 is in a condition of complete depletion, the depthof the depletion layer is only ‘h1’ and the width is only ‘d₁.’

[0060] Comparing FIG. 4 with FIG. 7, the ‘h2’ of FIG. 7 is larger thanthat of ‘h1’ in FIG. 4. The reason for this difference is that thethickness of the n⁻-diffusion layer of FIG. 7, which includes the firstn⁻-diffusion layer 23 a and the second n⁻-diffusion layer 23 b, is muchthicker than the conventional n⁻-diffusion layer 13. The n⁻-diffusionlayer 13 of the conventional method and the second n⁻-diffusion layer 23b of the present invention have the same depth and width.

[0061] In the embodiment of FIG. 7, a two-layer n⁻-diffusion layer isformed through a plurality of ion injections having different energylevels to form a thick n⁻-diffusion layer including the two-layers.Therefore, a depth and a width of the depletion layer are increasedwhen, operating a photodiode, and an area of a depletion layer isincreased, by increasing the depth and width of a photodiode depletionlayer electron generation and the photodiode storage area, therebyimproving light sensitivity of the image sensor of an incident light.

[0062] Thus, light (L) incident upon the photodiode PD′ and light (L₁₂,L₂₂) incident on other regions outside of the PD′ where the firstn⁻-diffusion layer 23 a extends will all be converted to image data. Thelight sensitivity of the image sensor is increased.

[0063] In the second embodiment, there is provided the p⁺-diffusionlayer 27 between the floating sensing node 26, that is an n⁺ dopedregion, and the first n⁻-diffusion layer 23 a, so when the firstn⁻-diffusion layer 23 a is completely depleted, an ion injection energyand depth of the first n⁻-diffusion layer 23 a will not be shorted. Thatis, the second embodiment restrains diffusion of change carriers fromthe first n⁻-diffusion layer 23 a to the floating sensing node 26.

[0064] Thus, in the second embodiment, there exist a processing marginfor the ion injection energy and depth control time used in forming thefirst n⁻-diffusion layer 23 a that prevents a shorting of the n⁺ dopedfloating sensing node 26 and the n⁻-diffusion layer 23 a when then⁻-diffusion layer 23 a is fully depleted.

[0065]FIGS. 8a to 8 d are cross-sectional views showing a manufacturingprocess to form a CMOS image sensor in accordance with the embodiment ofFIG. 7. Referring to FIG. 8a, p⁻-epitaxial layer 32 where a lowconcentration p-type dopant is doped is formed on a p⁺⁺ substrate 31where a high concentration p-type dopant is doped. The reason forgrowing the p⁻-epitaxial layer 32 is that the depth of the depletionlayer of a photodiode may be increased to obtain higher lightsensitivity through a low concentration p⁻-epitaxial layer 32. Also, thecross talk phenomena of a unit pixel caused by an irregular movement oflight electric charge, which may be generated from a deep portion of thep⁺⁺ substrate 31, is prevented through re-combination of light electriccharges with the existence of the high concentration p⁺⁺ substrate 31.

[0066] Next, a field insulating layer 33 for separating the unit pixelsis formed in a predetermined part of the p⁻-epitaxial layer 32 with alocal oxidation of silicon (LOCOS) method, and a photoresist layer iscovered on the resulting structure including the field insulating layer33.

[0067] The photoresist layer is selectively patterned to cover the fieldinsulating layer 33 and a first mask 34, which exposes the surface ofthe p⁻-epitaxial layer 32. After that, low concentration n-type dopantsare ion-injected with high energy to the p⁻-epitaxial layer 32 using thefirst mask 34 as an ion injection mask and then a first n⁻-diffusionlayer 35 having deep depth and wide area is formed.

[0068] Before forming the above-mentioned the field insulating layer 33and the first n⁻-diffusion layer 35, a p-well (not shown) is formed in apredetermined region of the p⁻-epitaxial layer 32, to include a drivegate (Dx) and a select gate (Sx), through a side diffusion by a thermaltreatment.

[0069] After forming the first n⁻-diffusion layer 35, a generaltransistor manufacturing process is carried out to form a drive gate(Dx) and a select gate (Sx) of the four transistors of unit pixel. Thatis, within the p-well, an ion injection process of a threshold voltagemodulating ion, which regulates threshold voltage of a transistor, and adeep ion injection process of a p-type dopant, which regulates apunchthrough characteristic, are performed. The ion injection processesare not performed in a region where the photodiode (PD′) and asource/drain of a transfer gate (Tx) are to be formed.

[0070] Referring to FIG. 8b, a first mask 34 is stripped and aconductive layer is deposited to form the four transistor gates of theunit pixel, and then a photoresist layer is covered and patternedthrough an exposure and development, thereby to form a photoresistpattern (not shown) for forming a gate electrode. At this time, a dopingprofile of a photodiode on one-side of a transfer gate (Tx) to beformed, determines an electric charge transfer effect. Accordingly, ahigh energy n-type dopant ion injection for forming a photodiode and alow-energy p-type dopant ion injection are arranged on one side of atransfer gate (Tx).

[0071] Next, the conductive layer is etched using a photoresist patternor etching mask for forming a gate electrode, and four gate electrodes36 of the unit pixel transistor are formed. The gate electrode 36 shownin FIG. 8B is a gate electrode of a transfer gate (Tx).

[0072] A photoresist layer is covered on the resulting structureincluding the gate electrode 36 and the second mask 37 for ion injectingand a high-energy n-type dopant is formed by selectively patterning thephotoresist layer. At this time, one-side of the second mask 37 isarranged in a center of a transfer gate (Tx), and the other side isarranged in a predetermined part of the field insulating layer 33,without entering in an active region.

[0073] Subsequently, a low concentration n-type dopant is ion injectedusing the second mask 37 as an ion injection mask, and the firstn⁻-diffusion layer 35 and the second n⁻-diffusion layer 38 are formed onone side (a photodiode side) of a transfer gate (Tx). The secondn⁻-diffusion layer 38 is formed by an ion injection energy, which ismuch lower than that of the first n⁻-diffusion layer 35, and the depth(thickness) is deeper and an area occupied by the p⁻-epitaxial layer 32is much wider than that of n⁻-diffusion layer 38.

[0074] A first deep pn junction may be formed in a low concentration ofthe p⁻-epitaxial layer 32 through the ion injection process that formsthe first n⁻-diffusion layer 35 and the second n⁻-diffusion layer 38.

[0075] Next, an ion injection process for forming source/drain of fourtransistor gates of a unit pixel is performed.

[0076] First, a photoresist layer is applied on the resulting structureand a third mask (not shown) is formed for forming a lightly doped drain(LDD) structure by patterning the photoresist layer with an exposure anddevelopment, and then, a low concentration n-type dopant is injectedusing the third mask as an ion injection mask within a p-well (notshown) to form the LDD region (not shown). The ion injection for formingthe LDD region is not performed in a region where the photodiode and twoof native transistors (Tx and Rx) are to be formed.

[0077] Referring to FIG. 8c, after removing the third mask, aninsulating layer is deposited on the resulting structure, and then theinsulating layer is blanket etched to form a spacer 39 contacting thesidewalls of the gate electrode 36.

[0078] Diffusion layers 40 a and 40 b are simultaneously formed on theexposed p⁻-epitaxial layer 32, including the second n⁻-diffusion layer38, and on the other side of the transfer gate (Tx) by a low energyp-type dopant (p⁰) blanket ion injection method. At this time, thep⁰-diffusion layer 40 a formed within the second n⁻-diffusion layer 38is isolated by the thickness of the spacer 39.

[0079] The p⁰-diffusion layers 40 b is ion injected with a lower energyp-type dopant, so a depth of the p⁰-diffusion layers 40 b has a shallowdepth. Therefore, the p⁰-diffusion layer 40 b is not in contact with thefirst n⁻-diffusion layer 35, but formed with p-type dopant, as with thep⁻-epitaxial layer 32.

[0080] A second shallow pn connection is formed comprising thep⁰-diffusion layers 40 a. The first and the second n⁻-diffusion layers35 and 38 are formed through the above-mentioned ion injection of p-typedopant, and then a pnp-type photodiode is formed from the p⁻-epitaxiallayer 32, the first and second n⁻-diffusion layers 35 and 38 and thep⁰-diffusion layer 40 a.

[0081] Referring to FIG. 8d, a photoresist layer is formed on theresulting structure and a fourth mask 41 is formed to form asource/drain region by patterning the resulting structure with anexposure and a develop process. A high concentration n-type dopant n⁺ ision injected using the fourth mask 41 as an ion injection mask to formn⁺-diffusion layer 42. As a result, two drive gates (Dx) of general NMOStransistor, a source/drain region (not shown) of a select gate (Sx), twotransfer gates (Tx) of general native NMOS transistor and a source/drainregion (a floating sensing node) of a reset gate (Rx) of the NMOStransistor are formed.

[0082] At this time, the fourth mask 41 exposes the other side of thetransfer gate (Tx) and the p⁻-epitaxial layer 32 around the other side,and the fourth mask 41 is arranged in a center of a transfer gate (Tx).That is, in a region where a photodiode is formed, a high concentrationn-type dopant is not ion-injected.

[0083] Next, a high concentration p-type dopant is ion-injected usingthe same fourth mask 41, and then a p⁺-diffusion layer 43 is formed on abottom portion of a ndiffusion layer 42 and on a upper portion of thefirst n⁺-diffusion layer 35. At this time, ion injection energy forforming the p⁺-diffusion layer 43 is bigger than that of then⁺-diffusion layer 42.

[0084] The above-mentioned p⁺-diffusion layer 43 has a highconcentration and it performs a different operation than thep⁻-epitaxial layer 32. For example, when the first n⁻-diffusion layer 35is completely depleted, the p⁺-diffusion layer 43 prevents then⁺-diffusion layer 42 and the first n⁻-diffusion layer 35 from shorting.After removing the fourth mask 41, a thermal treatment is carried out toactivate an ion-injected dopant.

[0085] An image sensor manufactured according to the above-mentionedsecond embodiment forms the first n⁻-diffusion layers 38, which forms aphotodiode over the whole area of a unit pixel, much longer and widerthan conventional devices, so an area of a photodiode is largelyextended.

[0086] The photodiode, which is largely extended in area, generateselectron charge carriers that not only represent incident light in aconventional photodiode, but also represent incident light received overthe entire area of a unit pixel.

[0087] In the second embodiment, after forming the n⁺-diffusion layer42, the p⁺-diffusion layer 43 is additionally formed to prevent a shortbetween the first n⁻-diffusion layer 35, which forms part of thephotodiode and the n⁺-diffusion layer 42, which forms the floatingsensing node.

[0088] In the above-mentioned first and second embodiment, all the imagesensors may be adapted to include a photodiode besides a CMOS imagesensor.

[0089] The above-mentioned embodiments increase a photodiode region,through a deeper depletion layer of a photodiode, to improve lightsensitivity to incident light. In addition, according to someembodiments, the area of the photodiode can be enlarged, therefore thedeterioration of electrical characteristics of the image sensor can beprotected by suppressing the short between the floating sensing node andthe n⁻-diffusion layer of the photodiode.

[0090] As one of ordinary skill in the art would understand from thedisclosed embodiments provided is a method of manufacturing an imagesensor having light sensitivity over a photodiode having an area equalto that of unit pixel.

[0091] Although the preferred embodiments of the invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

What is claimed is:
 1. An image sensor comprising: a first semiconductorsubstrate doped with a first conductive dopant; a first diffusion layerformed in the semiconductor substrate and doped with a second conductivedopant; a second diffusion layer formed in the semiconductor substrateadjacent the first diffusion layer and having a width wider than a widthof the first diffusion layer; a third diffusion layer doped with thefirst conductive dopant and formed at an exposed surface of thesemiconductor substrate in the first diffusion layer; a gate electrodeformed on the exposed surface and having a first edge adjacent to thethird diffusion layer; and a fourth diffusion layer doped with thesecond conductive dopant and formed at the exposed surface adjacent asecond edge of the gate electrode, the fourth diffusion layer defining agap with the second diffusion layer.
 2. The image sensor of claim 1,wherein a dopant concentration of the first diffusion layer is equal toa dopant concentration in the second diffusion layer, a dopantconcentration of the third diffusion layer is higher than the dopantconcentration of the first diffusion layer and a dopant concentration ofthe fourth diffusion layer is higher than the dopant concentration ofthe second diffusion layer.
 3. The image sensor of claim 1, wherein thefirst conductive dopant is a p-type dopant and the second conductivedopant is a n-type dopant.
 4. The image sensor of claim 1, wherein thegate electrode further comprises a first spacer between the first edgeof the gate electrode and the third diffusion layer and a second spacerbetween the second edge of the gate electrode and the fourth diffusionlayer.
 5. An image sensor comprising: a first semiconductor substratedoped with a first conductive dopant; a first diffusion layer formed inthe semiconductor substrate and doped with a second conductive dopant; asecond diffusion layer formed in the semiconductor substrate adjacentthe first diffusion layer and having a width wider than a width of thefirst diffusion layer; a third diffusion layer doped with the firstconductive dopant and formed at an exposed surface of the semiconductorsubstrate in the first diffusion layer; a gate electrode formed on theexposed surface and having a first edge adjacent to the third diffusionlayer; a fourth diffusion layer doped with the second conductive dopantand formed at the exposed surface adjacent a second edge of the gateelectrode, the fourth diffusion layer defining a gap with the seconddiffusion layer; and a fifth diffusion layer doped with the firstconductive dopant and formed between the fourth diffusion layer and thesecond diffusion layer.
 6. The image sensor of claim 5, wherein a dopantconcentration of the first diffusion layer is equal to a dopantconcentration in the second diffusion layer, a dopant concentration ofthe third diffusion layer is higher than the dopant concentration of thefirst diffusion layer, a dopant concentration of the fourth diffusionlayer is higher than the dopant concentration of the second diffusionlayer, and a dopant concentration of the fifth diffusion layer is higherthan the dopant concentration of the second diffusion layer.
 7. Theimage sensor of claim 5, wherein the first conductive dopant is a p-typedopant and the second conductive dopant is a n-type dopant.
 8. The imagesensor of claim 5, wherein the gate electrode further comprises a firstspacer between the first edge of the gate electrode and the thirddiffusion layer and a second spacer between the second edge of the gateelectrode and the fourth diffusion layer.
 9. The image sensor of claim5, wherein the third diffusion layer and the fourth diffusion layer havethe same width.
 10. A method of manufacturing an image sensor,comprising the steps of: a) forming a first diffusion layer within asemiconductor substrate, the semiconductor substrate being doped of afirst conductive dopant and the first diffusion layer being doped of asecond conductive dopant; b) forming a gate electrode on thesemiconductor substrate, the gate electrode having a first sidewall anda second sidewall; c) forming a second diffusion layer in thesemiconductor substrate adjacent the first diffusion layer; d) forming afirst spacer at the first sidewall and a second spacer at the secondsidewall; e) forming a third diffusion layer in the first diffusionlayer adjacent the first spacer, the third diffusion layer being dopedwith the first conductive dopant; and f) forming a fourth diffusionlayer within the semiconductor substrate adjacent the second spacer, thefourth diffusion layer being doped with the second conductive dopant.11. The method of claim 10, wherein a dopant concentration of the firstdiffusion layer is equal to a dopant concentration in the seconddiffusion layer, a dopant concentration of the third diffusion layer ishigher than the dopant concentration of the first diffusion layer and adopant concentration of the fourth diffusion layer is higher than thedopant concentration of the second diffusion layer.
 12. The method ofclaim 10, wherein an ion injection energy for forming the firstdiffusion layer is larger than an ion injection energy for forming thesecond diffusion layer and an ion injection energy for forming the thirddiffusion layer is smaller than an ion injection energy for forming thesecond diffusion layer.
 13. The method of claim 10, wherein the firstdiffusion layer and the fourth diffusion layer define a gap forpreventing a short when the first diffusion layer and the seconddiffusion layer are depleted.
 14. A method of manufacturing an imagesensor, comprising the steps of: a) forming a first diffusion layerwithin a semiconductor substrate, the semiconductor substrate beingdoped of a first conductive dopant and the first diffusion layer beingdoped of a second conductive dopant; b) forming a gate electrode on thesemiconductor substrate, the gate electrode having a first sidewall anda second sidewall; c) forming a second diffusion layer in thesemiconductor substrate adjacent the first diffusion layer; d) forming afirst spacer at the first sidewall and a second spacer at the secondsidewall; e) forming a third diffusion layer in the first diffusionlayer adjacent the first spacer, the third diffusion layer being dopedwith the first conductive dopant; f) forming a fourth diffusion layerwithin the semiconductor substrate adjacent the second spacer, thefourth diffusion layer being doped with the second conductive dopant;and g) forming a fifth diffusion layer between the fourth diffusionlayer and the second diffusion layer.
 15. The method of claim 14,wherein the fourth diffusion layer and the fifth diffusion layer areformed by ion injection using the same mask.
 16. The method of claim 14,wherein a dopant concentration of the first diffusion layer is equal toa dopant concentration in the second diffusion layer, a dopantconcentration of the third diffusion layer is higher than the dopantconcentration of the first diffusion layer, a dopant concentration ofthe fourth diffusion layer is higher than the dopant concentration ofthe second diffusion layer, and a dopant concentration of the fifthdiffusion.layer is higher than the dopant concentration of the seconddiffusion layer.
 17. The method of claim 14, wherein an ion injectionenergy for forming the first diffusion layer is larger than an ioninjection energy for forming the second diffusion layer and an ioninjection energy for forming the third diffusion layer is smaller thanan ion injection energy for forming the second diffusion layer.
 18. Themethod of claim 14, wherein an ion injection energy for forming thefourth diffusion layer is smaller than an ion injection energy forforming the fifth diffusion layer.